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NXP Semiconductors /LPC408x_7x /PWM0 /LER

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Interpret as LER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MAT0LATCHEN)MAT0LATCHEN 0 (MAT1LATCHEN)MAT1LATCHEN 0 (MAT2LATCHEN)MAT2LATCHEN 0 (MAT3LATCHEN)MAT3LATCHEN 0 (MAT4LATCHEN)MAT4LATCHEN 0 (MAT5LATCHEN)MAT5LATCHEN 0 (MAT6LATCHEN)MAT6LATCHEN 0RESERVED

Description

Load Enable Register. Enables use of updated PWM match values.

Fields

MAT0LATCHEN

Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7.
MAT1LATCHEN

Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details.
MAT2LATCHEN

Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details.
MAT3LATCHEN

Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details.
MAT4LATCHEN

Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details.
MAT5LATCHEN

Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details.
MAT6LATCHEN

Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data